数字电路测试压缩方法研究(英文)

New approaches to test compression for digital circuits

测试压缩可以在没有故障覆盖率损失的情况下,极大地降低测试时间和测试数据量,弥补了测试设备和芯片制造能力提升之间的差距,受到学术界和工业界的广泛关注.测试数据分为测试激励和测试响应2种,测试压缩也对应分为测试激励压缩和测试响应压缩2个方面.本文针对这2方面分别展开了研究.主要贡献包含:(1)提出了一种Variable-Tail编码.Variable-Tail是一种变长-变长的编码,对于X位密度比较高的测试向量能够取得更高的测试压缩率.实验数据表明,如结合测试向量排序算法,则使用Variable-Tail编码可以取得很接近于编码压缩理论上界的压缩效果(平均差距在1.26 %左右) ,同时还可以减少20 %的测试功耗.(2)提出了一种并行芯核外壳设计方法.研究发现了测试向量中存在着扫描切片重叠和部分重叠现象.当多个扫描切片重叠时,它们仅需要装载一次,这样就可以大大减少测试时间和测试数据量.实验结果表明,使用并行外壳设计,测试时间可以减少到原来的2/3 ,测试功耗可以减少到原来的1/15 .(3)提出了3X测试压缩结构.3X测试压缩结构包含了3个主要技术:X-Config激励压缩、X-Balance测试产生和X-Tolerant响应压缩.X-Config激励压缩提出了一个周期可重构的MUX网络.X-Balance测试产生综合考虑了动态压缩、测试数据压缩和扫描设计等因素,产生测试向量.它使用了回溯消除算法和基于确定位概率密度的扫描链设计算法,减少测试向量体积.X-Tolerant响应压缩提出了一种单输出的基于卷积编码的压缩电路.该压缩电路只需要一个数据,因此总能保证最大的压缩率.同时为了提高对X位的容忍能力,还提出了一个多权重的基本校验矩阵生成算法.

Test compression has drawn significant attention of academies and industries recently, since it can reduce test data volume and test application time of integrated circuits without losing fault coverage, thus diminishing the gap between the test and manufacture camps. Based on test stimulus and test response, the test compression techniques can be classified to two categories; test stimulus compression and test response compaction. This thesis conducts the research on both fields and presents several compression methods. The contributions of the thesis include： （1）This thesis presents a Variable-Tail code, and shows how to use this code to compress the test stimulus. Variable-Tail code is a variable- length-to-variable-length code, It can achieve higher test compression ratio in the case of high X-bit density. The experimental results show that the compression ratio of Variable-Tail with the proposed reordering algorithm is close to the theoretical upper bound of predictive codes （the average distance is only about 1.26% ）, while up to 20% of test power is saved. （2） This thesis presents the parallel core wrapper design. Studying on the distributions of X-bit, we find the phenomenon of full overlapping and partial overlapping of scan slices. When the slices overlap continuously, they can be loaded only once, thus test application time and test power are significantly saved. The experimental results show when the parallel core wrapper design is applied, compared with the serial core wrapper design, the test application time is reduced to 2/3 and test power is reduced to 1/15. （3）The 3X compression architecture is the main contribution of this thesis. The 3X architecture consists of three parts： X-Config stimulus compression, X-Balance test generation and X-Tolerant response compaction. X-Con_fig stimulus decompression uses a periodically alterable MUXs network. X-Balance test generation considers the dynamic compaction, compression, scan chain design and periodically alterable MUXs network as a whole. It applies two algorithms： one is the backward patterns remove algorithm and the other one is the specified bits based scan chain design algorithm. X-Tolerant response compaction uses a single-output compactor based on convolutional code. Since only one output pin is needed, X-Tolerant response compaction guarantees the highest compaction ratio. In order to achieve the X-Tolerant capacity, a multiple-weights basic check matrix generation algorithm is presented.