基于Single-Sequence布图规划边界约束问题的研究

The Boundary Constraints of Floorplanning Based on Single-Sequence

布图规划是VLSI设计中非常重要的步骤。在计算机辅助设计中,布图被表示成编码以使其容易被计算机处理。Single-Sequence就是一种非常有用的表示布图的编码方法。一个布图中,一些模块如输入输出模块,必须放置在芯片的边界处,这种限制被称为边界约束。本论文提出了用模拟退火算法寻求最优布图的方法,有效地解决了布图规划的边界约束问题。

The design of floorplanning is the most important step in the VLSI design. The floorplan is represented by codes in computer-aided design. Single-Sequence is a useful code representation. In a floorplan, some modules, such as Input/Output modules, must be placed on the boundary of chips, which is called the boundary constraint problem. In this paper, we propose a method for solving the boundary constraint problem and we seek the optimum solution by SA （Simulated Annealing） algorithm. It is proved that this method is useful and efficient in placement design with boundary constraints.