基于DDS的小数分频器的设计

Decimal Frequency Divider Design-Based on DDS

基于直接数字频率合成器DDS芯片AD9850的小数分频器设计,分频系数N是可以在限定范围内自行设置的任一小数,提出了三种不同计算输入时钟频率值的方法,并给出AD9850并行连接的源代码及实现小数分频器的基本结构框图,并对三个主要模块CPLD/FPGA、DDS(AD9850)和单片机(80C51)之间的连接加以详细的说明。

This paper introduces the design of the decimal frequency divider based on AD9850 which is a kind ot DDS＇ chip, and the frequency division coefficient can be set in one limited scope. It provides three different methods which calculate the value of the frequency of the input clock, and provides the sourse code of the AD9850 which works in the parallel ways. It gives the primary schematic and explains the connectivity of the three major modules CPLD/FPGA,AD9850 and 80C51 in details.