精确区分器件和互连寄生电阻电容的方法研究

Precise Distinction of Parasitic Resistance and Capacitance in Device and Interconnect of Integrated Circuit

随着器件线宽的不断缩小,在集成电路仿真中互连线延迟所占的比重逐渐变大,而MOSFET延迟所占的比重慢慢减小,这就意味着互连的寄生电阻电容对延迟的影响越来越大。研究了如何区分并计算器件部分和互连部分的寄生电阻电容。其中区分本地互连寄生电阻电容和器件电阻电容是关键。以90 nm器件为例,通过提取不同部分的寄生电阻电容,对环形振荡器进行延迟仿真,得到了它们对延迟的影响。通过不同的测试结构达到精确计算器件寄生电阻电容的目的,最终实现了对电路的精确仿真。

Interconnect delay plays a more and more important role in circuit simulation as devices scale down. It means that the ratio of parasitic RC （resistance and capacitance） of interconnect increases. How to distinguish and calculate the parasitic RC of device and interconnect was studied. And the key was to distinguish the parasitic RC of local interconnect and devices. The parasitic RCs at different parts of 90 nm devices were extracted, and the ring oscillator delay simulation was done and the impact on delay was found out. By some different test structures, the calculation of the device parasitic RC was realized more accurately, a more accurate circuit simulation was achieved.