基于FPGA卷积码和交织的实现

Implementation of convolutional code and interleaving based on FPGA

介绍了在QuartusⅡ软件平台上用VHDL语言和宏单元模块实现基于FPGA的(2,1,6)自正交系统卷积码和4×4行列交织器的一种方法,并对它们的工作和设计原理做了简单的介绍。最后,通过仿真测试验证了卷积码的纠错功能。还验证了原始数据经过交织后码字顺序发生改变,再经过解交织又恢复原来顺序的交织功能。

The article introduces a approach for FPGA implementation of the （2,1,6） system convolutional self-orthogoral code and 4 - 4 row-column interleaver with VHDL language and the components of LPM（library of parameterized modules） by utilizing the software-Quartus Ⅱ. The working and design theory of the approach is simply presented. Finally, the designs are simulated and tested.The results testify the system convolutional self-orthogoral code＇s rectify error capability and the fact that the original data change the sequence after interleaving and get the original sequence again after deinterleaving.