A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

用于CMOS图像传感器的9位10MS/s低功耗流水线ADC(英文)

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

提出了一个用于CMOS图像传感器的9位10MS/s、低功耗流水线ADC.为降低功耗,该设计通过采用低功耗、宽摆幅的带有增益增强结构的放大器以及将所有单元共用偏置电路的技术来实现.共用偏置技术需要仔细的版图设计和在电路中加入大的去耦合电容来实现.此外,设计中也采用电容阵列DAC来降低功耗.同时,为了增大信号处理范围,设计中还采用低阈值电压的MOS管.该ADC采用4M-1P的0.18μm CMOS工艺设计制造.对芯片的测试结果表明该设计的功耗仅为7mW,相对其他设计是相当低的.该ADC已经应用于30万像素图像传感器系统中,该系统已经流片、测试.