低杂散锁相环中的电荷泵设计

A Charge Pump Design for Low-Spur PLL

用TSMC0.18μm CMOS工艺设计并实现了一种电荷泵电路，传统的电荷泵电路中充放电电流有较大的电流失配,电流失配导致相位偏差,从而引起杂散并降低了锁相环的锁定范围，文中采用与电源无关的基准电流源电路,运用运算放大器和自偏置高摆幅共源共栅电流镜电路实现了充放电电流的高度匹配,从而降低了杂散。测试结果表明：电源电压1.8V时,电荷泵电流为0.475mA,在0.3-1.6V输出电压范围内电流失配小于10mA,功耗为6.8mW。

A charge-pump circuit that can be used in PLL is achieved through a TSMC 0.18μm CMOS process. Conventional CMOS charge pump circuits have large current mismatch. The current mismatch can generate a phase offset,which increases spurs in PLL outputs and reduces the locking range. An operational amplifier, self-biasing cascode current mirror, and supply- independent reference current source are used to make the charge and discharge current match. Measurement results show that the charge pump current is 0.475mA and the current mismatch is less than 10mA in the output voltage range of 0.3-1.6V,with power consumption of 6.8mW at 1.8V.