基于FPGA的磁盘阵列校验卡的设计与实现

Design and Implementation of a FPGA-Based RAID XOR Processing Engine

本文给出了一种采用Altera公司的Cyclone系列EP1C12Q240C8的FPGA芯片设计磁盘阵列校验卡的硬件电路的方法。该设计采用了并行的思想,令数据在PCI总线上的传输过程和校验计算过程在时间上重叠,使得整个校验过程耗费的时间等同于数据在总线上传输的时间,从而最大限度地提高了校验性能。设计经软件仿真和硬件实现,结果表明电路性能可靠。

This paper deals with the hardware design of a RAID XOR processing engine based on the EP1C12Q240C8 FPGA IC chip of the Altera Cyclone series.This design adopts the conception of parallelism.In order to provide the best performance,the parity check process is overlapped with the data transmission on the PCI bus,so the time spent on the whole task is equal to that of the data transmission on the PCI bus.Through software simulation and hardware implementation,the results indicate that the designed circuit is reliable.