并行CRC算法硬件实现研究与VHDL设计

Research the Hardware Implementation of CRC Parallel Algorithm with VHDL

介绍了循环冗余校验码(CRC)的生成算法,在分析讨论了几种常见CRC算法硬件实现的基础上,以VHDL给出了一种简单通用的CRC并行计算实现方法.该方法适用于各种不同的CRC生成多项式和各种不同的信息码宽度(如8位、16位、及32位等),经Altera公司的EDA开发工具软件QuartusII6.0编译、综合、优化、适配和仿真,得相关的时序仿真波形图、RTL图和占用硬件资源报告.分析各种数据报告可知设计意图得到了有效的贯彻.该设计最终还以杭州康芯公司GW48系列的SOPC/EDA实验开发系统所带的Cyclone系列中的EP1C12Q240C8芯片为硬件载体,经下载测试证实了设计的可靠性.

The generator algorithm of Cyclic Redundancy Check （CRC） are introduced, some familiar hardware implementations of CRC algorithm are analyzed,and the implementation of a simple and general prallel Cyclic Redundancy Code, or CRC computing are given with VHDL.It is suitable for any generator polynomial and any with of imformation codes between 1 and 32. We know that the design is successful by analyse those informations given by compile, synthesize, optimize, fit and simulate with QuartusII6.0, an EDA tool developed by Altera Company.We also know that the design works stable by validate its function with chip EP1C12Q240C8, which has design file downloaded inside.