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基于子矩阵移位法的大围数LDPC码设计 被引量:1

Design of LDPC Codes with Large Girth Based on the Submatrix Shifting Method
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摘要 通过分析LDPC码在Tanner图中的环在校验矩阵中形状的基础上,提出了四环、六环的检验算法。针对LDPC码的短环对码性能有重要影响,提出了1种围数为8的LDPC码的设计。算法首先对3个不同的子矩阵分别进行移位运算,每1个子矩阵与它们移位后生成的新的子矩阵共同组合生成1个新的子矩阵,然后将新生成的3个子矩阵组合成1个矩阵,最后将该矩阵转置后用单位矩阵以及单位矩阵的移位矩阵随机扩展即可得到校验矩阵。利用本文提出的校验矩阵所对应的生成矩阵对随机信息进行编码,在AWGN信道下的仿真结果表明具有逼近随机LDPC码的误码率性能。 By analyzing the shapes of 4-cycles and 6-cycles of TG in parity check matrix, this paper presents a method of counting the number of 4-cycles and 6-cycles. Considering the cycles, especially the short cycles, degrade the performance of LDPC decoders, this paper then proposes a design of regular check matrix for Low- Density Parity-Check (LDPC) codes with girth 8. The proposed construction algorithm for LDPC codes is to design 3 submatrices with different given shifting functions, then Combine them into one matrix, and finally expand the transposed matrix of the combination matrix into a desired parity check matrix using the identity matrix and the cyclic shift matrices of the identity matrix randomly. The simulation results in the AWGN channel show that the t3ER performance of these codes obtained by the generation matrix derived from the proposed check matrices in encoding the random information bits is as good as that of the random LDPC codes.
作者 范俊 肖扬
出处 《铁道学报》 EI CAS CSCD 北大核心 2007年第6期57-62,共6页 Journal of the China Railway Society
基金 国家自然科学基金资助项目(60572093)
关键词 通信 低密度奇偶校验码 奇偶校验矩阵 树图 检验算法 communication Low-Density Parity-Check(LDPC)codes parity-check matrices tree cycle check algorithm
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参考文献12

  • 1R G Gallager. Low-Density Parity Check Codes[D]. Cambridge, MA: MIT Press, 1963.
  • 2Y Kou, S Lin, M P C Fossorier. Low-density parity-check codes based on finite geometries: A rediscovery and new results[J]. IEEE Trans. Inform. Theory, 2001,47 (7) : 2711-2736.
  • 3R M Tanner. A recursive approach to low complexity codes [J]. IEEE Trans. Inform. Theory, 1981, 27(5): 533-547.
  • 4D J C MacKay, R M Neal. Near Shannon limit performance of low density parity check codes[J]. Electronics letters,1997, 33(6): 457-458.
  • 5D J C MacKay. Good error-correcting codes based on very sparse matrices[J]. IEEE Trans. Inform. Theory, 1999. 45(2):399-431.
  • 6R. Lucas, M Fossorier, Y Kou, S Lin. Iterative decoding of one step majority logic decodable codes based on belief propagation[J]. IEEE Trans. Commun. , 2000, 48 (6) : 931-937.
  • 7M. Sipser, D A Spielman. Expander Codes[J]. IEEE Trans. Inform. Theory, 1996, 42(6): 1710-1722.
  • 8N Wiberg. Codes and decoding on general graphs [D]. Linkoping, Sweden: Linkoping University, 1996.
  • 9J L Kim, U N Peled, I Perepelitsa, V Pies. Explicit construction of families of LDPC codes of girth at least six [C]// 40th Allerton Conf. Communication, Control and Computing, P G Voulgaris and R Srikant Eds. , Monticello, IL: Oct. 2-4, 2002, 1024-1031.
  • 10J Lu, J M F Moura, U Niesen. A class of structured LDPC codes with large girth[C]//Proc, of 2004 IEEE International Conference on Communications, 2004,1:425-429.

同被引文献9

  • 1GALLAGER R G. Low - density parity - check codes [ J ]. IRE Transaction on Information Theory, 1962, IT - 8 ( 1 ) : 21 -28.
  • 2IEEE. LDPC coding for OFDMA PHY. 802.16REVe sponsor ballot recirculation comment [ S ]. USA : IEEE ,2004.
  • 3DE - DIN. Digital video broadcasting ( DVB), second gener- ation:ET - SI EN 302 307 v. 1. 1, [S]. USA: DE - DIN ,2005.
  • 4MACKAY D J C, NEAL R M. Near shannon limit perform- ance of low density parity check codes. I J]. Electronics Let- ters, 1997,33 (6) :457 - 458.
  • 5WIBERG N. Codes and decoding on general graphs [ D ]. Linkoping, Sweden: Linkoping University, 1996.
  • 6MACKAY D J C. Good error - correcting codes based on very sparse matrices [ J ]. IEEE Transaction on Information Theo- ry,1999,45 (2) :399 -431.
  • 7MANSOUR M M, SHANBHAG N R. High - throughput LD- PC decoders [ J ]. IEEE Transaction on Very Large Scale In- tegration Systems ,2003 ( 11 ) :976 - 978.
  • 8SHIH Xinyu, ZHAN Chengzhou, LIN Chenghung, et al. An 8. 29 mm2 52 mW multi - mode LDPC decoder design for mo- bile WiMax system in 0. 13 I~m CMOS process [J]. IEEE Journal of Solid - state Circuits,2008,43 (3) :672 - 683.
  • 9张桂华,张善旭,李颖.高吞吐量低存储量的LDPC码译码器FPGA实现[J].西安电子科技大学学报,2008,35(3):427-432. 被引量:6

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