片上网络的功耗研究

Power Research of Network on Chip

随着芯片上晶体管数量发展到10亿数量级,功耗逐渐成为芯片设计的首要制约因素。本文分别从CMOS电路和网络通讯两个层面上来分析片上网络(NoC)的功耗,并给出了相应的功耗模型。利用不同的功耗模型,从物理方法、软件方法、网络拓扑三个方面来研究NoC的功耗设计问题。

With the development of the billion-transistor chips, power is becoming increasingly the first-order constraint of the design. In this paper, we compare two power models, in terms of different levels,CMOS-level and network-level. Then, we research the problems of NoC power using methods of physics, software programming and network Topologies according to the two power models.