基于CPLD的CCD驱动时序电路设计

Design of the Time Sequence Driving Circuit for CCD Based on CPLD

为了克服早期电荷耦合器件CCD驱动电路体积大、设计周期长、调试困难等缺点,提出利用复杂可编程逻辑器件CPLD,结合硬件描述语言VHDL,实现线阵CCD的驱动时序电路设计。通过在Max+PlusⅡ平台下对驱动时序仿真,并进行实际测量,结果表明该设计方案实现了对CCD器件的时序驱动。

To improve the defects of big cubage, complicated design and diffcult debug in driving circuit for CCD, a method of using CPI.D and VHDI. together to design the time sequence driving circuit for a kind of liner CCD is presented, Simulate time sequence driving circuit on Max＋Plus Ⅱ ,and test it practically. The result indicates that the design of the time sequence for CCD is accurate.