期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

基于总线共享架构的片上多处理器系统性能探索 被引量：3

Exploring Performance of Shared-Bus-Based Multi-Processor System on a Chip
下载PDF
导出
摘要 采用SystemC建立了一个基于共享总线的MPSoC仿真平台,设计了3个实验分别用于建模3种典型应用(低计算/通讯比、高计算/通讯比和非独立任务),对系统性能进行了详细的调研。实验结果显示:处理器数≤6时,总线架构MPSoC体现出很高的效率,而处理器数=16几乎达到了总线架构MPSoC适用规模的极限;计算/通讯比对性能和规模有重要影响;流水线方案能略微缓解通讯状况。建议:处理器数≤6时,推荐采用总线方案;6<处理器数≤16时,总线方案是否合适由任务计算/通讯比决定;处理器数>16时,需要采用更高级的通讯方案。 Shared-bus based multi-processor system on a chip （MPSoC） is one of the most popular solutions to multimedia application featured as parallel computation. Otherwise, sequential assess mechanism of bus imposes limitations and negative effects on the performance and scale of MPSoC. So, it is very meaningful to explore the performance of Shared-bus based MPSoC. In this paper, we setup a MPSoC simulation platform based on shared-bus and carry out a lot of experiments on the platform. As a result, we get a conclusion about the efficiency of the MPSoC and the impact of applications on performance improvement of MPSoC. It demonstrates bus-based MPSoC shows high efficiency when N≤ 6 and almost reaches its limit when N=16.
作者 杨盛光 李丽 徐懿 张宇昂 张冰
机构地区 南京大学微电子设计研究所 南京大学江苏省光电信息功能材料重点实验室
出处 《微电子学与计算机》 CSCD 北大核心 2007年第12期16-19,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(90307011 60576034 60373076)
关键词 片上多处理器系统 总线 加速比 单核效率 总线占用率 MPSoC bus speedup efficiency per core bus busy rate
分类号 TP393.02 [自动化与计算机技术—计算机应用技术]
  • 相关文献

参考文献7

  • 1Poletti F, Bertozzi D, Benini L, et al. Performance analysis of arbitration policies for SoC communication architectures [A]. Design Automation for Embedded Systems [C]. 2003: 189-210
  • 2Charles Bo-Cheng Lai, Patrick Schaumont. Energy and performance analysis of mapping parallel multithreaded tasks for an on-chip multi-processor system [C]. Proceedings of the 2005 International Conference on Computer Design, California, 2005
  • 3Pierre G Paulin, Chuck Pilkington. Parallel programming models for a multiprocessor SoC platform applied to networking and Multimedia [J]. IEEE Transacctions on Very Large Scake Integration (VLSI) Systems, July 2006, 33 (7): 667-680
  • 4Chiara Francalanci, Paolo Giacomazzi. High-performance self-routing algorithm for multiprocessor systems with shuffle interconnections [J]. IEEE Transactions on Parallel and Distributed Systems, 2006, 17 (1): 38N50
  • 5陈绍贺,赵明,王京.基于SystemC的片上系统设计[J].微电子学与计算机,2005,22(4):51-52. 被引量：11
  • 6王峥,李德识,曹阳,张俊新.基于SystemC的AMBA总线模型的构建与验证[J].微电子学与计算机,2004,21(12):1-3. 被引量：3
  • 7Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane. Extending the transaction level modeling approach for fast communication architecture exploration [C]. DAC '04, San Diego, California, USA, 2004

二级参考文献14

  • 1Open SystemC Initiative. SystemC 2.0 User Guide. http: //www.systemc.org.
  • 2Kalavade A, Lee E A. Global Criticality/local Phase Driven Algorithm for the Constrained Hardware/ Software Partitioning Problem. In Proc 3nd IEEE Int. Workshop. Hardware/Software Co-design, Sept. 1994: 42～48.
  • 3Jantsch A, Ellervee P, Hemani A. Hardware/Software Partitioning and Minimizing Memory Interface Traffic. In.IEEE/ACM Proc. European Conf. Design Automation(EuroDAC), Sept. 1994: 220～225.
  • 4R Emst, J Henkel, T Benner. Hardware-software cosynthesis for microcontrollers. IEEE Design and Test of computers,Dec.1993, 10(4): 64～75.
  • 5Ken Chapman. PicoBlaze 8-bit Microcontroller for Virtex-E and Spartan-Ⅱ/ⅡE Devices. Xilinx, XAPP213 ,February,2003.2.
  • 6Rashinkar P, Paterson P. System-On-A-Chip Verification Methodology and Techniques [M] ..Kluwer Academic Publishers Group,2002.
  • 7Stan Y. Towards a new standard for system-level design [A]. Proceedings of the eighth international workshop on Hardware/software codesign[C]. San Diego, California, United States: ACM Press, 2000: 2～6.
  • 8Semeria L, Ghosh A. Methodology for Hardware/Software Co-verification in C/C++[A]. Asia and South Pacific Design Automation Conference ASP-DAC'00[C].Yokohama:ACM Press ,2000: 405～408.
  • 9Sudeep P. Transaction Level Modeling of SoC using SystemC 2.0 [A]. Synopsys User Group Conference'02 [C].Bangalore: Kluwer Academic Publishers, 2002:11～15.
  • 10ARM Limited. AMBATM Specification (Rev2.0) [EB/OL].http://www.arm.com, 1999-5-13.

共引文献10

同被引文献15

  • 1陈绍贺,赵明,王京.基于SystemC的片上系统设计[J].微电子学与计算机,2005,22(4):51-52. 被引量：11
  • 2周文彪,张岩,毛志刚.片上通信结构——共享总线和NoC的分析与比较[J].计算机工程与应用,2007,43(15):121-124. 被引量：5
  • 3Pasricha S, Bozorgzadeh N, Ben - Romdhane E, et al. Floorplan-aware automated synthesis of bus-based communication architectures[C]//Proceedings of the 42nd annual conference on Design automation 2005. Anaheim, California, USA: IEEE, 2005 : 565 - 570.
  • 4Paulin Pierre G, Pilkington Chuck. Parallel programming models for a muhiprocessor SoC platform applied to networking and multimedia [ J ]. IEEE Transactions on very large .scale integration(VLSI) Systems, 2006, 33 (7) : 667 - 680.
  • 5Arteris. A comparison of network - on - chip and busses [EB/OL]. [2005 - 12 - 10]. http://www. arteris. com.
  • 6Sudeep Pasricha, Nikil Dutt, Mohamed Ben - Romdhane. Extending the transaction level modeling approach for fast communication architecture exploration [ C ]// DAC' 04. San Diego, California, USA: IEEE, 2004:113-118.
  • 7李耀荣,王兴军,梁利平.SOC总线仲裁算法的研究[J].微计算机信息,2007,23(17):113-115. 被引量：11
  • 8马立伟.专用片上网络没计方法:通信建模、拓扑构造与动生成[D].北京:清华大学,2006.
  • 9QIAN Yue, LU Zhong-hai, DUO Wen-hua. Analysis of worst-case delay bounds for best- effort communication in wormhole netsworks on chip [C]//NoCS 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip. Sail Diego, CA: ACM, 2009 : 44-53.
  • 10张曼.百万门级SoCj占片深亚微米物理设计的方法[D].上海:复旦大学,2010.

引证文献3

二级引证文献1

微电子学与计算机
2007年 第12期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部