32位稀疏树加法器的设计改进与实现

Modification and Implementation of 32-Bit Sparse Tree Adder

提出了一种改进进位运算的32位稀疏树加法器。在对现有稀疏树加法器使用的进位运算算子"o"进行深入探讨的基础上,对该算子的表达式做出了适当改进,去除了原算子中进位输入须为0的前提条件,同时保留了原算子适用于稀疏树进位结构的运算特性。采用该改进算子的32位稀疏树加法器可以并行地产生进位输入分别为0和1时的一对"和"输出,并可根据需要选择输出相应的结果。在1.2V130nm典型CMOS工艺条件下,经由HSPICE仿真,改进的32位稀疏树加法器的关键路径延迟为10.8FO4。结果表明,该加法器在运算能力得到扩充的同时,在运算速度方面也具有一定优势。

A 32-bit sparse tree adder with modified carry tree structure is proposed. Based on principle of ＂o＂ operation, the carry operator of proposed adder is modified to eliminate the constraint on carry input, while maintaining non-redundant tree structure of existing sparse adders. This enables calculating possible sum output in both cases of carry input ZERO and ONE in parallel before obtaining final sum bits according to specific situation. The proposed 32- bit sparse tree adder is implemented and simulated in typical 1.2V 0.13μm CMOS technology and achieves a critical path delay of 10.8 FO4, which indicates that the proposed adder is applicable considering its increased capability and speed.