一种并行指令Cache的设计与实现

Design and Implement of a Parallel Instruction Cache

为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。设计了高速并行指令Cache的系统架构,将Cache体访问与线形地址到物理地址的地址转换并行操作,成功实现一个时钟周期内完成地址转换和指令读出的设计目标。详细设计了Cache体和TLB的逻辑结构,并对相关设计参数进行了精心规划,并在设计中采用了奇偶校验逻辑增加了芯片的可靠性。此结构应用于JX微处理器流片成功,并工作可靠正确。

To improve the operating efficiency of general micro processors, the architecture and design method of instruction cache are investigated. A new kind of the system architecture of a high-speed parallel instruction Cache is designed. Accessing to the memory body and address changing from a linear address to the physical one are realized to work synchronously. The logic structures of the Cache body and TLB are made out, and those design parameters are planed in detail. The parity check logic is adopted to enhance the reliability of chips. This Cache structure is taped out successfully, and works correctly and reliably, applied in the JX microprocessor.