双STC时钟恢复电路的设计与实现

Design and implementation of a two-STC clock recovery circuit

针对数字电视机顶盒的重要功能——多节目解码对播放同步的需求,设计了一种双时钟计数器(STC)的时钟恢复电路,并在支持先进音视频编码标准(AVS)的高清解码芯片中得到实现。该电路使用主从两个STC,主STC由一个混合型的锁相环驱动,该锁相环产生的27MHz时钟同时用于产生音视频解码时钟;从STC则由一个全数字的锁相环驱动,它仅用于与展示时间戳(PTS)比较产生显示同步控制信号。同时提出了一个硬件的低通滤波算法,该算法保证了STC在稳态下追踪传输流中的节目时钟参考(PCR)的变化,并且提供稳定的时钟输出,同时有效降低了主控CPU的负荷。仿真实验结果表明,所提出的时钟恢复电路和低通滤波算法具有较好的性能和较低的计算复杂度,并有效地降低了硬件开销。

In order to meet the synchronization requirement of multi-stream decoding, an important function of a digital TV settop box, a two-STC clock recovery circuit was designed and implemented in the HDTV decoding chip for advanced coding standard of audio and video （AVS）. It contains a primary system time-clock counter （STC） and a secondary STC. The primary STC is driven by a mixed-signal phase-locked loop counter （PLL）, the 27 MHz output clock of which is used to generate the clock of video and audio decoder. The secondary STC is driven by an all-digital PLL, which is only used to be compared with the presentation time stamp （PTS） to generate synchronization signal for presentation. A hardware-oriented low-pass filter algorithm was also proposed. The algorithm enables the STC to track the change of the input program clock reference （PCR）, and ensures a stable output clock. It also greatly reduces the load of the host CPU. The simulation result shows that the proposed circuit and its hardware-oriented low-pass filter algorithm have good performance, low computational complexity, and low silicon cost.