LDPC编码的FPGA实现

Realization of FPGA for LDPC encoding

低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码,它的直接编码运算量较大,通常具有码长的二次方复杂度.为此,利用有效的校验矩阵,来降低编码的复杂度,同时研究利用大规模集成电路实现LDPC码的编码.在ISE 8.2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程,为LDPC码的硬件实现和实际应用提供了依据.

Low-density parity-check code（ LDPC code） is a kind of linear error-correcting code nearest to Shannon Limit. For LDPC code, the computational overhead for direct encoding operations is large, as the complexity of encoding is the square of the length of eodeword. Hence, this paper reduces the complexity of coding by using effective parity-check matrix, and realizes the encoding device for LDPC code by use of large-scale integrated circuits. The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8.2 software platform, providing a feasible basis for hardware implementation and practical application of LDPC code.