T4快速以太网HUB数据转发器设计及FPGA实现

The repeater design of T4 fast Ethernet HUB and implementation in FPGA

用VHDL语言设计了100BASE-T4快速以太网HUB中数据转发器电路;分析了基于CSMA/CD协议的T4快速以太网HUB物理子层数据编码和传输机制;硬件结构包括端口控制电路、仲裁电路、时钟多路选择器电路、FIFO电路、核心控制电路、标志生成输出多路选择器电路;用MAX+PLUSⅡ软件进行了仿真调试和器件下载测试,结果表明该电路系统实现了数据转发目的并且满足CSMA/CD物理子层协议的要求。

The repeater of 100BASE-T4 fast Ethernet HUB is designed with VHDL, The data coding and transmitting mechanism on physical sublayer of T4 HUB based on CSMA/CD are analyzed. The whole circuits include port control circuit, arbiter, clock MUX, FIFO, core control circuit, and symbol generation ＆ MUX. The design is simulated in MAX＋PLUS Ⅱ tools and downloaded to a proper FPGA device. The results demonstrate it realizes the repeating function and meets the demand of physical sublayer in CSMA/CD.