VLSI流水化格型数字滤波器的内建自测试

Built-In Self-Test for VLSI Pipelined Lattice Digital Filter

格型数字滤波器在信号处理领域得到了广泛应用,本文针对VLSI实现的流水化格型数字滤波器,提出了一种内建自测试方案,不需要对其内部基本功能单元作任何更改,且能在较短时间内检测所有的单固定型故障.所有测试序列都采用简单的算术运算产生.通过对已有功能模块如累加器的复用,作为测试序列生成和响应压缩,该方案能实现真速测试并最大程度的减少了硬件占用和系统性能占用.

Lattice digital filter chips are widely used in many signal processing applications.We propose a built-in self-test （BIST）scheme for VLSI pipelined lattice digital filter chips which needs no modification of the basic building cells and all the single stuck-at faults can be detected in reasonable time.All the test vectors can be generated by simple arithmetic operation.By reusing available arithmetic function units such as accumulators to generate test vectors and compact test responses,such scheme can be implemented at-speed with minimum hardware overhead and performance degradation.