锁相环频率合成器中分频器设计

Design of Divider for PLL Frequency Synthesizer

从工程的角度出发,设计两个应用于锁相环频率合成器的可编程分频器电路,一个采用脉冲吞除技术的可编程分频器,另一个是具有新颖结构,能实现1:1占空比的奇数分频器。同时,详细研究了分频器设计中的关键问题。最后,采用1stSilicon0.25um的CMOS混合信号工艺对分频器电路进行了仿真,仿真结果表明分频器设计的正确性。

The tow programmable dividers is designed from the viewpoint of engineering for PLL frequency synthesizer. The programmable frequency divider with pulse swallow technique is investigated. Another novel odd frequency divider with 1:1 duty rate is designed. The key questions in divider design are researched. The circuits are implemented using 1st Silicon 0.25μm mixed-signal Complementary Metal-Oxide-Semiconductor (CMOS) process. Simulation results show that the design of dividers are correct.