CMOS 5 Gb/s串行接收器

CMOS 5 Gb/s Receiver

设计了一个使用0.13μm CMOS工艺制造的低电压低功耗串行接收器。它的核心电路工作电压为1V,工作频率范围从2.5 GHz到5 GHz。接收器包括两个1:20的解串器、一个输入信号预放大器以及时钟恢复电路。在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度。测试表明,接收器功耗45 mW。接收器输入信号眼图闭合0.5UI,信号差分峰-峰值150 mV条件下误码率小于10^(-12)。接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。

A low voltage and low power receiver implemented in 0.13 μm CMOS process is described. The power supply voltage is 1V and the operating frequency range is from 2.5 GHz to 5 GHz. The receiver employs two 1 -＂ 20 deserializers, an input signal pre-amplifier and clock and data recovery circuit. The pre-amplifier uses a novel architecture consisting of a feed-forward equalizer to cancel ISI. Measured receiver power consumption is 45mW. The test results indicate the receiver BER is less than 10-12 when input signal amplitude is 150 mV differential peak-topeak and eye closure is 0. 5UI. An improved coding pattern is also employed in phase interpolator to reduce the phase nonlinearity and generate constant amplitude of sampling clock.