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薄外延层RESURF LDMOS完全耐压模型 被引量:2

A Full Breakdown Model of Thin Epitaxial RESURF LDMOS
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摘要 提出硅基薄外延RESURF LDMOS不全耗尽和完全耗尽的完全耐压模型。基于求解二维Poisson方程,获得该结构二维表面电场和击穿电压的完整解析表达式。借助此模型研究击穿电压与器件结构参数、外延层掺杂浓度和衬底掺杂浓度的关系;在满足最优表面电场和完全耗尽条件下,得到器件优化的RESURF判据。解析结果、MEDICI数值结果和实验结果吻合较好,验证了模型的准确性。 A full analytical breakdown model for thin epitaxial RESURF LDMOS is presented in this paper. Based on the 2-D Poisson equation, the derived model gives the solutions of the surface field distributions and breakdown voltage of completely-depleted and partially-depleted LDMOS. Based on this model we calculate the influence of all design parameters on breakdown voltage. Under condition of optimal surface electrical field and depleted completely, the RESURF condition is obtained. All analytical results are well verified by the numerical analysis of MEDICI and experiment.
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2007年第4期540-544,共5页 Research & Progress of SSE
关键词 薄外延 完全 击穿电压 模型 thin epitaxial full breakdown voltage model
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参考文献11

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同被引文献10

  • 1孟坚,高珊,陈军宁,柯导明,孙伟锋,时龙兴,徐超.用阱作高阻漂移区的LDMOS导通电阻的解析模型[J].Journal of Semiconductors,2005,26(10):1983-1988. 被引量:4
  • 2李琦,李肇基,张波.薄外延阶梯掺杂漂移区RESURF耐压模型[J].固体电子学研究与进展,2006,26(1):1-5. 被引量:2
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  • 4ERLBACHER T, BAUER A J, FREY L. Reduced on resistance in LDMOS devices by integrating trench gates into plana technology [ J ]. IEEE Electron Device Letters, 2010,31 ( 5 ) :464 - 466.
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  • 6HE Jin, ZHANG Xing. Quasi-2-D analytical model for the surface field distribution and optimization of RESURF LDMOS transistor [ J]. Microelectronics Journal ,2001,32:655 - 663.
  • 7WU Jie, FANG Jian, ZHANG Bo, et al. A novel double RESURF LDMOS with multiple rings in non-uniform drift region[ C ] //Proc of IEEE ICSICT. Piscataway : IEEE ,2004:349 - 352.
  • 8SHEU Gene, LIN Yinghuang, TSENG Wenchin, et al. Comparison of high vohage(200 - 300vohs) lateral power MOSFETs for power integraed circuits[J]. ECS transactions on Design and Device Engineering,2010,27( 1 ) :103 - 108.
  • 9李琦,李肇基.电阻场板LDMOS表面电场解析模型及优化设计[J].固体电子学研究与进展,2008,28(2):185-189. 被引量:1
  • 10GUO Yu-Feng,WANG Zhi-Gong,SHEU Gene,CHENG Jian-Bing.A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques[J].Chinese Physics Letters,2010,27(6):179-182. 被引量:2

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