双时钟输入的Cache-AMBA桥设计

Design of Cache-AMBA Bridge with Two-Clock Input

设计了一种适用于不同时钟域之间数据传递的Cache-AMBA桥。利用AHB总线的信号特点以及桥与I-Cache和D-Cache控制器的握手机制,用较简单的组合逻辑解决了数据的丢失及数据的重复采样问题。SoC系统通过了FPGA原型验证,并用TSMC 0.25μm CMOS工艺流片成功。芯片测试结果表明,系统在CPU与总线频率之比为2∶1和1∶1两种模式下均正常工作,CPU的最高频率为133MHz。

A Cache -AMBA bridge design used to transfer datum in two frequency input is presented. Signal characteristic of AHB bus and handshake mechanism between bridge and Cache system are utilized adequately in design. A simple combinational circuit is imposed to solve datum loss and repeat sample. The bridge is embedded into SoC system which is verified by FPGA prototype and approved by TSMC with 0.25p, m CMOS process. The test result shows the chip works smoothly with two frequency input. The CPU frequency reaches 133MHz.