基于FPGA的RS译码器实现

Implementation of RS Decoder Based on FPGA

RS码以强大的纠错能力得到广泛的应用,以往的译码器的硬件实现总是很复杂,资源利用较多,译码周期也较长。文中采用Blahut算法,先用MATLAB进行了软件仿真,并验证了算法的正确性,然后用FPGA实现了RS(31,15)译码器的设计。在硬件设计中优化了原来的电路结构,减少了一个迭代周期,从而一定程度上提高了译码器的译码速度,而FPGA实现复杂度也较低。

RS code is widely used because of its very strong correcting ability. Many RS decoders have been improved, but they are too complexity and occupies a lot of hardware resources. In other hand, it takes a long period to decode a code. In this paper, Blahut algorithm is introduced. The algorithm is first simulated by MATLAB, The simulation shows that the algorithm is right. Then, the RS（31,15） decoder is implemented by using the algorithm on a FPGA chip. The decoder structure is modified in some sense to decrease delay. The structure is easy for implementation based on FPGA.