ESD应力下的NMOSFET模型

NMOSFET Model Under ESD Stress

随着现代集成电路的集成度越来越高,静电放电(Electrostatic Discharge,ESD)己成为电路失效一个不可忽视的原因。对电路级ESD的可靠性进行模拟是一个重要的研究课题。给出了在ESD应力下的NMOSFET模型,重点讨论了雪崩击穿区、瞬间回落区,以及二次击穿区的物理过程及其数学描述。

As more and more devices are integrated into a single chip, electrostatic discharge （ESD） has become one of the major concerns in IC malfunction. Therefore, simulation of the ESD reliability in the cirbuit level is of great importance. An NMOSFET model under ESD stress is presented, and the physical process and mathematic description of the avalanche breakdown area, snapback area and the secondary breakdown area are discussed in particular.