动态可重构高速缓存结构的研究与设计

Study and Design of Dynamically Reconfigurable Cache Architecture

提出了一种动态可重构高速缓存结构,提升了系统性能;同时,大大降低了功耗。该结构在传统高速缓存上作少量的硬件改动,实现了高速缓存容量、块大小和关联度的动态可配置性。实验结果表明,相对于传统结构,动态可重构高速缓冲存储器在不损失性能的前提下,取得了很好的降低系统功耗的效果。

A dynamically reconfigurable cache architecture was presented to make compromise between performance and energy consumption. With little modification to conventional architecture, the newly developed architecture can be reconfigured by itself with regard to a three-dimensional space, namely, cache capacity, line size and associativity. Experimental results show that the reconfigurable cache architecture improves the performance in a more energy-efficient way, compared with the conventional one.