基于遗传算法的分割可测试设计

Genetic Algorithm Based Partition Design For Test(DFT)

基于遗传算法,建立了片上系统芯片(SOC)的图模型,对逻辑级的SOC结构进行精确量化;然后,对模型应用遗传算法进行分析,得到了电路的理想分割结果;最后,基于分割结果,实现一颗SOC的可测试设计(DFT).实验结果表明,在分割的均匀度与附加电路代价方面,该方法相比原有的DFT方法有显著的改进.

A genetic algorithm based low power design for test （DFT） method was presented to reduce the power consumption of a system-on-chip （SOC） significantly during the test. This method overcomes the own restriction of normal partition based DFT, such the by-product cost and uncontrollable partition resuits. Firstly, a graphic model is established for the general SOC to obtain the accurate quantisation. Then the genetic algorithm is applied to the graphic model to obtain an optimized partition. At last, the DFT on an SOC is implemented based on the partition results. The simulation results show that the remarkable improvement is obtained in the respects of cost of the extra circuit and the rationality of partition.