VHDL语言高级综合子集的确立及其实现方法

THE DETERMINATION OF A VHDL SUBSET FOR HIGH LEVEL SYNTHESIS AND ITS IMPLEMENTATION METHODOLOGY

越来越多的高级综合系统采用或接受ＶＨＤＬ语言作为设计输入，但ＶＨＤＬ语言的语义本质是基于模拟而非基于高级综合的，许多语法现象不能或不适于进行综合．本文系统地分析了ＶＨＤＬ语言的可综合性问题，详细讨论了ＶＨＤＬ语言的各种语法现象的可综合性，并结合实际系统分析了ＶＨＤＬ语言高级综合子集的确立及实现方法．

More and more high level synthesis systems accept VHDL as design input. The simulation based semantics of VHDL, however, causes many difficulties for synthesis. This paper analyses the synthesizability of VHDL systematically, discusses in detail the various synthesizability problems of VHDL syntax. The implementation methodology of VHDL high level synthesis is given.