基于SOPC的边界扫描测试控制器开发

Development of boundary-scan test controller based on SOPC

本文阐述了一种新颖的基于SOPC边界扫描控制器的设计,提出了一种更加灵活、高效的嵌入式系统新解决方案。该方案将边界扫描测试子系统嵌入在Altera公司推出的低成本、高密度、具有嵌入式NIOS软核CPU的CycloneⅡ系列的现场可编程阵列(FPGA)上,大大提高了系统设计的灵活性、边界扫描的测试效率。同时开发的具有自主知识产权的JTAG控制IP核模块为SOPC系统提供了一个颇有实用价值的组件,无需专用边界扫描测试设备即可实现系统的边界扫描测试功能。详细论述了基于SOPC的边界扫描控制器设计及JTAG总线控制IP核模块的开发。仿真及实验结果表明,此设计正确合理,能够进行有效的边界扫描测试。

The paper describes an original design of Boundary Scan Test System based on SOPC and brings up a more flexible and effective embedded system solution, which makes use of SOPC technology. This scheme integrates multiple function modules on a low cost and high density FPGA, which is developed with embedded NIOS CPU by Altera Company, including boundary-scan test module. It improves the flexibility of design, testing efficiency of boundary scan system and speed rate of fetching data. At the same time, JTAG bus controlling IP core that has own intellectual property provides a valuable module for SOPC system. The design of boundary-scan test controller based on SOPC and the development of JTAG bus controlling IP core are presented in detail. The simulation and experimental results have proved the design correct and rational, and are capable of processing boundary-scan test effectively.