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工业ESD模拟设备波形校准及校准实例 被引量:1

Industrial ESD simulator waveform verification and practical verification case
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摘要 本文阐述了如何根据业界相应的标准对ESD模拟装置进行波形校准,先给出了工业进行ESD测试的背景,然后简要介绍了一种较为常见的ESD静放电形式——HBM(人体放电模式)——产生以及其在工业中进行波形校准的基本原理和所需设备,并对如何正确架设调整校准设备,如何进行有关静放电模拟器和测量板的校准程序进行了探讨,最后以HBM+1kV短路波形校准为实例进行了更进一步的说明。结果表明通过架设校准电路以及设定正确的波形校准程序,同时以业界的明确的标准为规范,相关技术人员就可以对ESD模拟设备产生的静放电波形进行校准。 The paper illustrates how to carry out a ESD waveform verification on the ESD simulator. First of all, the paper presents the background of industrial ESD test. Then we introduce the generation of a common ESD mode HBM as well as the principle and equipment of the waveform verification in industrial application, illustrate the right method of installing the adjusting verification device, and discuss the verification programme of ESD simulator and measuring panel. Finally we present a practical HBM +1kv short circuit waveform verification procedure as an example. Results show that with the verification circuit installed and the right waveform verification programme as well as the specific industrial criteria, relevant technicians can correctly perform the ESD waveform verification for ESD simulation devices.
作者 王昊鹏 胡明
出处 《电子测量技术》 2007年第12期148-151,共4页 Electronic Measurement Technology
关键词 静电放电 波形校准 人体放电模式 ESD waveform verification HBM
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参考文献9

  • 1ESD STMS. 1. ESD Association Standard Test Method for Electrostatic Discharge Sensitivity Testing Human Body Model Component Level [S]. ESD Association, 2001.
  • 2JESD22-A114-B. JEDEC Standard for Electrostatic Discharge (ESD) Sensitivity Testing Human Body Modal (HBM) [S]. JEDEC Solid State Technology Association, 2001.
  • 3AEC-Q100-002-REV-F. AEC Standard for Human Body Model Electrostatic Discharge Test [S]. Automotive Electronics Council Component Technical Committee, 2003.
  • 4JOACHIM C. Relevance of Contact Reliability in HBMESD Test Equipment[J].Microelectronics Reliability , 2001,41 (9-10):1397-1401.
  • 5VERHAEGE K. Justifications for Reducing HBM and MM ESD Qualification Test Time[J].Microelectronics Reliability, 1996,36 : 1715-1718.
  • 6HUANG C Y,CHEN W F,CHUAN S Y,et al. Design Optimization of ESD Protection and Latchup Prevention for A Serial I/O IC[J].Microelectronics Reliability , 2004,44, : 213-221.
  • 7BARTH J, RICHNER J, HENRY L G, et al. Real HBM and MM Waveform Parameters[J].Journal of Electrostatics, 2004,62, : 195-209.
  • 8GRUND E. A Wafer I.evel HBM Tester Delivering Pulses with Variable Risetime through Transmission lines [J].Journal of Electrostatics, 2004,62 : 99-112.
  • 9POMMERENKE D. Ninth International Sysmp[Z]. On High Voltage Engineering(9th ISA), 1995:7740.

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