LD-CELP编解码器的ASIC设计

ASIC Design of LD-CELP Coding

LD-CELP可以全面满足16 kb·s^(-1)算法的性能要求,已被广泛应用在会议电视系统、IP电话等领域。基于此规范,采用Verilog HDL硬件描述语言完成RTL级设计,所有编解码结构都由Verilog实现的DSP en- gine完成,并对最佳码书序号进行了压缩处理,解决了最佳码书序号的比特浪费问题。系统物理测试采用FPGA验证方式。验证结果表明,系统功能完全正确,可实现实时编解码过程,解码语音具有良好可懂度。

LD - CELP can satisfy all the performance requirements of 16Kbps algorithm, and has been widely applied in video conference systems, IP phones and other fields. According to this standard, the paper implements an RTL level design of speech coding using Verilog HDL. All the structures in the coding process are performed by DSP engine realized by Verilog HDL. Speech compression of the best coding index optimizes the consumption of bit. Physical test of coding system are implemented through FPGA verification, which shows that the coding system functions well, and is capable of real - time speech coding and decoding with good e- nough distinctiveness of voice.