期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

组合电路中逻辑错误诊断方法研究 被引量：1

Research of logic error diagnosis in combinational circuits
下载PDF
导出
摘要 介绍了近些年出现的几种错误诊断方法,它们在传统方法的基础上利用启发式对原有方法进行了不同程度的改进和提高,产生了较好的诊断结果。 This paper introduced some error diagnosis methods occurred in these years. These methods enhanced the traditional methods by using some heuristics, and achieved the better diagnostic results.
作者 齐芳 吴尽昭 闫炜 徐德启
机构地区 兰州大学信息科学与工程学院 中国科学院成都计算机应用研究所
出处 《计算机应用研究》 CSCD 北大核心 2008年第1期114-116,共3页 Application Research of Computers
基金 国家自然科学基金资助项目(60373113) 国家“973”计划资助项目(2004CB-318000)
关键词 诊断 路径追踪 模拟 可满足性 diagnosis path-trace simulation SAT
分类号 TP306 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献11

  • 1BOPPANA V,MUKHERJEE R,JAIN J,et al.Multiple error diagnosis based on Xlists[C]//Proc of the 36th ACM/IEEE Design automation Conf.New York:ACM Press,1999:660-665.
  • 2VENERIS A,HAJJ I N.Design error diagnosis and correction via test vector simulation[J].IEEE Trans on Computer-Aided Design,1999,18(12):1803-1816.
  • 3ANAND L,SOUZA D',HSIAO M S.Error diagnosis of sequential circuits using region-based model[C]//Proc of IEEE VLSI Design Conf.2001:103-108.
  • 4LI Guang-hui,SHAO Ming,LI Xiao-wei.Design error diagnosis based on verification techniques[C]//Proc of the 12th Asian Test Symposium.Xi'an:[s.n.],2003:474-477.
  • 5SMITH A,VENERIS A,VIGLAS A.Design diagnosis using boolean satisfiability[C]//Proc of Asia South Pacific Design Automation Conf.2004:218-223.
  • 6CHUNG P Y,WANG Y M,HAJJ I N.Logic design error diagnosis and correction[J].IEEE Trans on VLSI System,1994,2(3):320-332.
  • 7VENERIS A G,HAJJ I N.A fast algorithm for locating and correcting simple design errors in VLSI digital circuits[C]//Proc of Great Lake Symposium on VLSI Design.1997:45-50.
  • 8POMERANZ I,REDDY S M.On diagnosis and correction of design errors[J].IEEE Trans on Computer-Aided Design,1995,14(2):255-264.
  • 9WAHBA A M,BORRIONE D.A method for automatic design error location and correction in combinational logic circuits[J].Journal of Electronic Testing:Theory and Applications,1996,18(2):113-127.
  • 10VENKATARAMAN S,FUCHS W K.A deductive technique for diagnosis of bridging faults[C]//Proc of IEEE/ACM Int Conf Computer Aided Design.New York:ACM Press,1997:562-567.

同被引文献12

  • 1刘卓军,吴尽昭.集成电路验证技术[J].中国基础科学,2007(3):11-14. 被引量：3
  • 2Anand L, Souza D, Hsiao M S. Error Diagnosis of Sequential Circuits Using Region - Based Model[A]. Proceedings of IEEE VLSI Design Conference[C]. 2001 : 103 - 108.
  • 3Shi- Yu Huang. Speeding up the Byzantine Fault Diagnosis Using Symbolic Simulation[A]. 20th IEEE VLSI Test Symposium[C]. 2002.
  • 4Boppana V,Mukherjee R,Jain J,et al. Multiple Error Diagnosis Based on Xlists[A]. Proceedings of Design Automation Conference[C]. 1999: 100 - 110.
  • 5Nandini Sridhar, Hsiao M S. On Efficient Error Diagnosis of Digital Circuits[A]. Proceedings of International Test Conference[C]. 2001 : 678 - 687.
  • 6Li Guanghui,Shao Ming, Li Xiaowei. Design Error Diagnosis Based on Verification Techniques [A]. Proceedings of the 12th Asian Test Symposium[C]. 2003:7 081 - 7 735.
  • 7Jain A, Boppana V, Mukherjee R, et al. Verification and Diagnosis in the Presence of Unknowns[A]. 18th VLSI Test Symposium[C]. 2000 : 263 - 269.
  • 8Smith A,Veneris A,Viglas A. Design Diagnosis Using Boo- lean Satisfiability[A]. ASPDAC[C]. 2004:218- 223.
  • 9Prasad M R,Biere A,Gupta A. A Survey of Rencent Advances in SAT - based Formal Verification[J]. Int'l Journal on Software Tools for Technology Transfer ,2005,7(2) :.156 - 173.
  • 10Zeng Z,Talupuru K R,Ciesielski M. Functional Test Generation Based on Word - level SAT [J]. Journal of Systems Architecture, 2005,51 (8) : 488 - 511.

引证文献1

计算机应用研究
2008年 第1期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部