一种基于FPGA的新型误码仪设计

Design of new type bit error tester based on FPGA

本文设计主要分为误码仪硬件电路的设计和FPGA内部功能的软件设计两个部分,硬件设计主要是FP-GA的外围电路设计,RS232电路设计,E2PROM电路设计以及按键和指示灯等;软件设计主要是实现了传输速率在1～24MHz内8种速率可调、29-1位、215-1位、223-1位3种序列长度的伪随机码码型可选、可手动发送误码、误码检测以及FPGA片外资源总体控制等误码仪主要功能。

There are mainly 2 part designs in this paper, hardware design and software design which based on FPGA. The hardware design is mainly about the circuits around FPGA, RS232 circuits, E^2 PROM circuits, key and led layout designs. Software design are realized some functions like 8 level speed control during 1 to 24 MHz, 3 code type to choose 2^9 - 1,2^15 - 1,2^23 - 1, sent error code manually, bit error rate test and some other resources control around FPGA, and so on.