亚65nm静态随机存储器稳定性提高技术

Sub-65 nm SRAM Stability Improvement Techniques

CMOS工艺进入到65nm节点后,工作电压降低,随机掺杂导致阈值电压变化增大,给SRAM的读写稳定性带来挑战。介绍了目前业界最新的主要稳定性提高技术。双电源电压、直流分压、电荷共享和电容耦合通过改变字线或者存储单元电压来提高读写稳定性,这些技术都采用外加读写辅助电路来实现;超6管存储单元通过在传统6管单元上增加晶体管,有效提高了读写稳定性;三维器件FinFET构成的SRAM具有传统器件无法比拟的高速、高稳定性、面积小的特点。对这些技术的优缺点作了分析比较。

SRAM read and write stability is challenged by the scaling CMOS technology beyond the 65-nm node due to a decrease in power supply voltage and an increase in threshold variation caused by the random doping. Latest techniques for improving stability, including dual power, DC division, charge sharing and capacitance coupling, were presented. With a read and write assist circuit （RWAC） employed, the above four techniques can improve the read and write stability by lowering or raising the levels of word line and cell power terminal VSRAM.The new structure SRAM cell, which had more than 6 MOSFETs, achieved higher stability due to the added MOSFET. The SRAM composed of 3D FinFETs is charaterized by high speed, high stability and low area penalty, which are not available for conventional SRAM.