形态算子的位串法实现

The Realization of Morphological Operators by the Bit serial Approach

作者在灰度ＦＰ形态算子的最大最小表示的基础上给出了它们的位串实现结构。论文说明了灰度ＦＰ形态算子可以通过一个二进制处理电路的ｋ次叠代使用而实现，此处ｋ为输入信号二进制码的位数，其硬件复杂度为Ｏ（ｋ）．该数字实现结构上简单且模块化，适合ＶＬＳＩ实现。

This paper presents a bit serial implementation architecture for the gray scale morphological FP(function processing) operators based on their max/min representations. It is shown in the paper that gray scale morphological operators can be realized by the k step recursive use of one binary processing circuit, where k is the number of bits in the input signals. The time area complexity of the proposed filtering operators is O(k). The proposed digital realization is simple and modular in sturcture, suitable for VLSI implementations.