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基于VHDL的简易数字频率计的设计与实现

Design and Realization of Digital Frequency Meter Based on VHDL
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摘要 针对复杂大规模可编程器件的特点,提出了一种新的数字频率计的实现方法。在MAXPLUSII开发软件环境下,采用硬件编程语言VHDL,实现了数字频率计的设计。经过仿真,并下载验证,能够实现测频功能。 In view of the complex large-scale programmable component's characteristic, proposed one kind of new digital frequency meter realizes the method. L'nder the MAXPLUSII development software environment, uses hardware programming language VIIDL, has realized the digital frequency meter's design. After the simulation, and downloads the confirmation, can realize the frequency measurement function.
出处 《科技广场》 2007年第11期230-231,共2页 Science Mosaic
关键词 VHDL 频率计 仿真 VHDL Frequency Meter Simulation
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参考文献1

  • 1宋万杰等.CPLD技术及其应用[M]西安电子科技大学出版社,1999.
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