摘要
文章讨论几种全加器的设计,并设计了一种基于数据选择器的全加器。通过HSPICE仿真,与其他结构的全加器进行比较,结果表明基于数据选择器的全加器在功耗与速度上比其他结构的全加器有较大提高。
Full adders are discussed, and a multiplexer based full adder is designed. HSPICE simulation shows that the multiplexer based full adder consumes less power and has higher speed compared with the other adders.
出处
《电子与封装》
2008年第1期29-32,共4页
Electronics & Packaging