32位高性能浮点乘法器芯片设计研究

Chip Design of High-performance 32-bit Floating-point Multiplier

介绍了FFT(快速傅里叶变换)系统中32位高性能浮点乘法器的芯片设计。其中24位定点乘法部分采用两种不同的结构进行对比:经典的阵列式结构和改进Booth编码的树状4∶2列压缩结构,后者提高了乘法器的性能。整个设计采用Verilog HDL语言进行RTL(寄存器传输级)描述,并在QuartusⅡ平台下完成了FPGA(现场可编程门阵列)仿真验证,然后结合synopsys逻辑综合工具DesignCompiler以及TSMC 0.18μm CMOS工艺库完成了综合后仿真。最后,将综合后得出的网表送入后端设计工具Apollo进行了自动布局布线。本次设计采用流水线技术,系统时钟频率可达250 MHz。

A chip design of high performance 32-bit floating-point multiplier in FFT system is presented. Two structures are used for designing the 24-bit fixed-point multiplier. One is the classical structure using array and the other is the structure using 4：2 column compression trees with the modified Booth encoding. The second structure improves the performance of floating-point multiplier. The whole system is described in Verilog HDL and simulated by QUARTUS Ⅱ. And then, the design is synthesized with TSMC 0.18 μm library in synopsys DC. At last, the netlist generated by synthesis is sent to Apollo for layout. With the technology of pipeline, the frequency of the system can reach 250 MHz.