一种用于逐次逼近ADC的低电压高准确度比较器

A Low Voltage and High Resolution Comparator for Successive Approximation ADC

设计了一种用于逐次逼近结构ADC中的低电压比较器,比较器由前置开关预放器和动态锁存器组成。前置放大器完成对输入信号进行放大,其高增益提高了比较器的准确度,动态锁存器的正反馈提高了比较器的速度。采用了0.6μm CMOS工艺设计,工作于2.5 V单电源电压,通过详细的电路原理分析和软件SMATSPICE的仿真,得到的分析和仿真结果说明该比较器具有速度快、准确度高、功耗小的特点,适用于逐次逼近结构中的低电压模数转换器。

A low voltage comparator for successive approximation Analog to digital converter（ADC） is designed. It consists of switched preamplifier and dynamic latch. Amplifying of the input signal can be achieved by preamplifier. High gain improves the accuracy of the comparator and positive feedback increased the speed of it. The design is based on 0.6 μm CMOS the power voltage is the single 2.5 V. The analysis of circuit theory and the simulation based on the SMARTSPICE softw, results indicate that the comparator has the merits of high speed, high resolution and low-power. The circuit is applicable to successive approximation low-voltage ADC.