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基于总线功能模型的SoC仿真加速技术 被引量:1

SoC Simulation Speed-up Technology Based on Bus Functional Model
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摘要 SoC是IC设计的发展趋势,而随着SoC的日趋复杂,对系统仿真带来了越来越艰巨的挑战,基于EDA厂商提供的传统仿真环境已经不能充分满足SoC的开发需求,针对此问题提出了基于总线功能模型的仿真加速策略,测试结果表明,提出的技术策略可获得45%的仿真性能提升。 SoC is becoming the trend of IC design. With the ever-increasing complexity of SoC, there are more and more arduous challenges facing system simulation process during SoC development. And the traditional simulation platform provided by EDA vendors can not satisfy SoC designers' need. In this paper, a simulation speed-up strategy is presented to solve this problem with the experimental results which show that this strategy can accelerate the simulation speed in 45 percent.
出处 《微电子学与计算机》 CSCD 北大核心 2008年第1期45-47,51,共4页 Microelectronics & Computer
基金 国家“八六三”计划项目(2002AA1Z1040) 中科院计算所创新课题(20056170) 北京市工业促进局技术发展资金项目(京财经一指[2005]1858号)
关键词 仿真加速 SOC 验证 总线功能模型 CPU simulation speed-up SoC verification bus functional model CPU
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  • 1Greeg D Lahti, Tim L Wilson. Designing Procedural-Based Behavioral Bus Functional Models for High Performance Verification, SNUG, 1999.
  • 2Synopsys. Inc, PCI/PCI-X FlexModel User's Manual, 2003,5.
  • 3Janick Bergeron. Writing Testbenches-Functional Verification of HDL Models, Boston, Kluwer Academic Publisher,2000.
  • 4The Unified Verification Methodology, 2003, www.candence.com
  • 5Rindert Schutten ,Tom Fitzpatrick. Design for Verification [R]. Synopsys. April,2003
  • 6韩俊刚、杜慧敏,数字逻辑的形式化验证,北京:北京大学出版社,2001.
  • 7Bergeron Janick, Writing Testbenches: Functional Verification of HDL Models, Kluwer Academic Publishers, 2000.
  • 8Harry Foster and Lionel Benning, Principle of Verifiable Verilog Design, Kluwer Academic Publishers, 2000.
  • 9Stefen Boyd, Using Vera to Test a DMA Engine, http:∥www.open-vera.com/technical/technical.html
  • 10韦乐平,光同步数字传送网,北京:人民邮电学院出版社,1998.

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