一种适于16位RISC处理器的伪四级流水结构研究

Study of Pseudo-4-Stage Pipeline for 16bit RISC CPU

提出了伪四级流水结构概念,并在一种微处理器控制器中实现运用。该结构可以在显著提高微处理器指令执行速度的同时,简化其中程序控制器的设计复杂度,降低对芯片资源的要求,适合应用于一些面向I/O数据处理或中低档控制等级的微处理器/微控制器场合。该结构技术已获得国家发明专利授权。

This paper introduces the conception of a pseudo-4-stage pipeline architecture and implements it in the controller of a microprocessor. By this means, the executing speed of instruction for microprocessor can be improved evidently, while the design complexity of the controller of a microprocessor be simplified greatly, and chip＇s area be reduced. It is very fit to the applications of microproeessor/microeontroller oriented to I/O data processing and middle or low level industry control. This pseudo-4-stage pipeline architecture has gained the national invention patent authorized by the SIPO.