一种高度并行无乘法器结构的二维IDCT协处理器设计

A Design of 2D-IDCT Coprocessor Based on Highly-Parallel Multipilerless Architectures

介绍了一种适用于MPEG-4视频简单层解压缩应用的二维IDCT协处理器。该处理器采用Loeffler架构的IDCT快速算法,并使用加法和移位运算代替IDCT快速算法中的浮点乘法运算单元,用高度并行流水VLSI结构加快数据处理速度,采用一维的IDCT单元的复用的方式来实现二维的IDCT运算。在满足处理速度和精度要求的基础上,利用较少的晶体管数目实现了一种高性能的二维IDCT处理器。该方案已经应用于一款SOC芯片中的硬件MMA(多媒体加速单元)中,IDCT的运算精度也得到了验证。

In this article, the BINIDCT algorithm, a fast approximation of the Discrete Cosine Inverse Transform and its efficient VLSI architectures for hardware implementations with Wishbone bus are presented. The design is focused on a multiplierless 1D-IDCT. The realization is applicable to the 2D-IDCT algorithm. The designed lifting parameters are given in this article. With its high performance and low power consumption features, the 2D-IDCT coprocessor is an excellent candidate for real-time IDCT-based image and video processing applications.