高速低功耗传输电路的时钟系统设计

A Clock Generator for High Speed and Low Power Parallel Link

利用锁相环(PLL)为高速低功耗并行传输电路发射机生成时钟信号的系统。设计了一个稳压器(Voltage Regulator),为PLL中对噪声敏感的模块提供低噪声的电压源。在此基础上提出了一种新型的动态改变工作频率的方法,应用于源同步(source-synchronous)模式的高速传输电路。此方法可以在不改变PLL状态的情况下快速改变输入输出(I/O)电路的工作频率,降低功耗。整个芯片采用0.18μm CMOS工艺设计并流片测试成功。

A dock generator using PLL for high speed and low power parallel link is presented. The PLL is designed with a voltage regulator which provides a clear supply voltage for the noise sensitive blocks. A new method is explored to generate clocks for dynamic frequency switching of the high speed link which works in source-synchronous mode. This method can switch the working frequency of the I/O circuits quickly without changing the state of the PLL block. The whole chip has been designed and fabricated in the 0.18μm CMOS technology.