摘要
中值滤波广泛用于图像处理领域,但用硬件实现时,占用资源过大.本文介绍了一种基于位级运算的中值滤波硬件实现,并给出了其电路结构.这种方法使得硬件资源和输入数据的位宽成线性关系.最后借助Altera公司的Cyclone系列FPGA芯片EP1C12和Quartus II6.0开发软件对设计进行了仿真验证.
Media filter is widely used in digital image processing, but being realized in hardware will take too many resources. This paper introduces a hardware design method of media filter based on bit level algorithm. Then it is simulated using the EP1C12 of the Cyclone series chips and the software of Quartus 116.0.
出处
《首都师范大学学报（自然科学版）》
2007年第6期27-29,共3页
Journal of Capital Normal University：Natural Science Edition
