期刊文献+

分布式同步的GALS片上网络及其接口设计 被引量:6

GALS Network-on-Chip with a distributed-synchronous mechanism
原文传递
导出
摘要 为了降低数据的传输延迟,提出了一种分布式同步方式实现全局异步局部同步(GALS)片上系统。该方式通过引入时钟来实现相邻网络节点之间的数据传输,使数据传输最小延迟由原来无时钟通信方式的4个线延迟减少到1个线延迟,大大降低了数据传输延迟。同时设计了支持该方式的跨时钟域接口。该接口不仅支持多路数据在同一物理链路中传输,而且允许在每个传输周期动态分配各路数据的带宽。仿真结果表明:支持4通道和16位宽数据的接口总共占用722个ALUT(adaptive look-up table)和支持204.5 MHz的时钟速率,占用较少面积和支持较高的时钟速率。 A distributed-synchronous mechanism was developed to implement globally asynchronous locally synchronous (GALS) Network-on-Chip to reduce transport latency. This mechanism enables clock control data transport in the control of clock, so the minimum transporting delay can be reduced from 4Δ (wire delay) to 1Δ. An asynchronous interface was designed to support the distributed-synchronous mechanism. The asynchronous interface supports multiple channels, enables dynamic bandwidth allocations between channels in every data transport cycle. An interface with four 16 bit channels required 722 adaptive look-up tables and ran at 204.5 MHz. Simulation results show that the interface supports high data rate at reasonable complexity.
出处 《清华大学学报(自然科学版)》 EI CAS CSCD 北大核心 2008年第1期32-35,38,共5页 Journal of Tsinghua University(Science and Technology)
基金 国家自然科学基金资助项目(90607009)
关键词 片上网络 分布式同步 全局异步局部同步 network on chip distributed-synchronous globally asynchronous locally synchronous
  • 相关文献

参考文献9

  • 1Ivanov A, De Micheli G. The network-on-chip paradigm in practice and research [J]. Design & Test of Computers, 2005, 22(5): 399-403.
  • 2Saleh R. An approach that will NoC your SoCs off![J]. Design & Test of Computers, 2005, 22(5) : 488 - 488.
  • 3Pande P P, Grecu C, Ivanov A, et al. Design, synthesis, and test of networks on chips[J]. Design & Test of Computers, 2005, 22(5) : 404 - 413.
  • 4Gupta R. On-chip networks [J].Design & Test of Computers, 2005, 22(5) : 393 - 393.
  • 5Rostislav D, Vishnyakov V, Friedman E, et al. An asynchronous router for multiple service levels networks on chip [C]// Asynchronous Circuits and Systems. New York City USA: IEEE Press, 2005:44-53.
  • 6Najibi M, Saleh K, Naderi M, et al. Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs [C]// Rapid System Prototyping. Montreal Canada: IEEE Press, 2005:63-69.
  • 7Muttersbach J, Villiger T, Fichtner W. Practical design of globally-asynchronous locally-synchronous systems [C]// Advanced Research in Asynchronous Circuits and Systems. Eilat, Israel: IEEE Press, 2000:52-59.
  • 8Moore S W, Taylor G S, Cunningham P A, et al. Self calibrating clocks for globally asynchronous, locally synchronous systems [C]// Computer Design Proceedings. Los Alamitos: IEEE CS Press, 2000:73 - 78.
  • 9Villiger T, Kaslin H, Gurkaynak F K, et al. Self-timed ring for globally-asynchronous locally-synchronous systems [C]// Asynchronous Circuits and Systems. Vancouver BC, Canada: IEEE Press, 2003:141 - 150.

同被引文献87

  • 1徐阳扬,周端,杨银堂,王青松,廖峰.非对称GALS系统异步接口设计[J].西安电子科技大学学报,2007,34(2):294-297. 被引量:7
  • 2王宏伟,陆俊林,佟冬,程旭.层次化片上网络结构的簇生成算法[J].电子学报,2007,35(5):916-920. 被引量:4
  • 3Rostislav D, Vishnyakov V, Friedman, et al. An Asynchronous Router for Multiple Service Levels Networks on chip [ C]// Proceedings of the 11 th IEEE International Symposium on Asynchronous Circuits and Systems. New York: IEEE CS Press, 2005: 44-53.
  • 4Asghari S A, Pedram H, Khademi M. A Flexible Design of Network on Chip Router based on Handshaking Communication Mechanism [ C] //Proceedings of the 14'h International CSI Computer Conference. Tehran: IEEE CS Press, 2009: 225-230.
  • 5Arun J. Networks-on-Chip Based High Performance Communication Architectures for FPGAs [ D]. Ohio: Univ of Cincinnati 2008.
  • 6Lu Z, Jantsch A. Admitting and Ejecting Flits in Wormhole-Switched Network on Chip [ J]. IET Computer &Digital Techniques, 2007, 1(5) : 546-556.
  • 7Cumings C E. Simulation and Synthesis Techniques for Asynchronous FIFO Design[ C/OL]. [ 2010-9-6]. http://www, sunburst- design, corn/papers/.
  • 8Apperson R W, Zhiyi Y, Meeuwsen M J, et al. A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains [ J]. IEEE Trans on VLSI Systems, 2007, 15( 10): 1125-1134.
  • 9Samman F A, Hollstein T, Glesner M. Flexible Parallel Pipeline Network-on-chip Based on Dynamic Packet Identity Management [ C]//Proceedings of the 2008 IEEE International Parallel & Distributed Processing Symposium. New Jersey: IEEE, 2008: 1-8.
  • 10Jung H, Hwang A, Pedram M. Predictive-flow-queue-based energy optimization for gigabit ethernet controllers [J].IEEE Transactions on Very Large Scale Integration Systems, 2009, 17(8): 1113-1126.

引证文献6

二级引证文献12

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部