浮点协处理器设计及其在电力电子数字控制平台中的应用

Design of a Floating-point Coprocessor and Its Applications in Digital Platform for Power Electronics

由于定点数字信号处理器(digitalsignalprocessor,DSP)存在字长效应和运算能力不足的问题,在一些电力电子应用场合不得不采用浮点DSP。为了解决定点DSP的电力电子数字控制平台的计算瓶颈问题,该文提出了用现场可编程逻辑阵列配置浮点协处理器的方法来提升平台的计算能力。该文给出了浮点运算单元的详细设计过程,并提出了一种更为简单的浮点除法算法实现方法,该算法的误差分析表明:最大绝对值误差不超过2个最小位。仿真和实验验证该浮点协处理器的运算速度可达2.5千万次浮点运算。用快速傅里叶变换算法测试运算效率的实验表明:浮点协处理器的运算效率比DSP算法运算效率快5倍之多。

Due to the problem caused by word effect and computation capacity of fixed-point DSPs, floating-point DSPs have to be adopted in some power electronic applications. In order to relieve the bottleneck of computation in the digital platform based on fixed-point DSP for power electronic systems, the paper proposed a new architecture to enhance the computation capacity of this kind digital platform by configuring a floating-point coprocessor using FPGA（Field Programmable Gate Array）. Detailed design procedures of the coprocessor are presented, and a novel simplified algorithm for floating-point division is proposed. Error analysis of the proposed algorithm shows that the maximum absolute approximate error is less than 2ulp（Unit in Last Place）. The coprocessor speed can reach up to 25 MFLOP（Million Floating-point Operations）. FFT（Fast Fourier Transform） algorithm is adopted to test the computational efficiency of the floating-point units. Experimental results show the computation time by FPU is five times less than that of DSP algorithms.