摘要
本文中，针对规则的VLSI设计模式（门阵列，标准单元等），我们提出一种新的非常简单有效的布局算法．该算法基于严格的数学分析，可以证明能够找到全局最优解．在实验中发现，对于很大规模的电路，我们的算法比现有的所有算法都快．此外，我们的算法还能够同时适应于线长优化和时延优化模式．
For regular ICs, a novel VLSI placement algorithm is presented. The algorithm is based on strict mathematical analysis, can provably find the global optima. And the algorithm's requirements for system resource are rather low. Experimental results are very promising. For a test circuit avq with scale large up to 21000 cells, our algorithm is faster than any existing algorithms. Another point is that our algorithm is suitable for timing driven placement.
基金
国家攻关经费基金
高等学校博士学科点专项科研基金
关键词
VLSI
设计
VEAR
全局优化
Algorithms
Integrated circuit layout
Integrated circuits
Optimization
Time series analysis
