Turbo编码器的FPGA实现

FPGA Implementing of Turbo Encoder

采用FPGA实现CDMA2000系统的Turbo编码器。其交织器由一个同步双口RAM和一个ROM构成。RAM存放输入待编码的数据,ROM作为交织地址的查找表。数据输入期间,由输入数据有效表示有数据输入,进行输入同步,此时往RAM里写数据,ROM不进行操作,一个数据帧向RAM写完后开始由ROM中读出数据作为交织地址,从RAM中取出编码所需的数据。RAM的写地址由控制时序电路contrl模块提供,读RAM的地址由ROM的输出提供,而读写控制即读写使能也都是由控制时序电路contrl模块进行控制。

Use FPGA to realize the Turbo coder of CDMA2000 system. Its interlace instrument consists of a synchronization dual-port RAM and a ROM. The RAM stores the input coding data and the ROM is the search list of interlace address. When inputting data, the input data effectively displays the data input and carries out input synchronization. At the same time, write data to RAM, the ROM stops. After writing, a data frame reads a data from ROM as interlace address, and acquires useful data for coding. The time control module provides RAM with written address. The ROM output provides address for reading RAM. The read ＆ write control is managed by the control module.