一个面积优化的高速RS(255,239)译码器VLSI设计

Area-efficient high-speed VLSI design of the RS(255,239) decoder

基于改进的Euclid算法,提出了一种仅含两个折叠计算单元的结构,并用三级流水线结构整体实现以提高吞吐率.将常规有限域乘法器转化到复合域中实现,降低了芯片的复杂性和关键路径延迟.以RS(255,239)为例,基于TSMC 0.18标准单元库的译码器电路规模约为20 614门,在相同纠错能力下,该结构相比较于传统的并行脉动阵列结构,其硬件复杂度可减少60%左右.

Based on the modified Euclid＇s algorithm, a VLSI architecture is proposed, which only uses two folding calculating cells and three-stage pipeline processing architectures to improve its throughput. Also, a way is introduced to reduce the complexity and critical path delay of general finite multipliers by the transferring of field from the time domain to the composite domain. Based on the TSMC 0. 18 standard cell library, the proposed RS decoder consists of about 20 614 gates for widely used RS（255, 239） code, which reduces complexity by about 60% compared with an existing architecture with systolic arrays when having the same error correction ability.