采用多级子并行滤波器级联结构的并行FIR滤波器

The Parallel FIR Filter with the Cascade Structure of Multi-stage Parallel Sub Filters

在并行FIR的快速迭代短卷积算法(ISCA)基础上,采用多级小尺寸并行FIR结构级联结构,实现了一种新型并行FIR滤波器。在增加一定量的加法器和延迟单元等弱运算强度单元的情况下,大大减少使用的乘法器数量。一个采用3级(2×3×6)级联结构的2并行36抽头FIR滤波器仅需18个乘法器,比单级ISCA算法实现的FIR结构节省了67%,更适合于专用并行FIR滤波器的VLSI实现。

A new parallel FIR filter based on the iterated short-convolution algorithms （ISCA） is designed with the structure of multi-stage small size parallel sub FIR filters. The parallel FIR filters with this new structure will significantly diminish the number of multiplies at the cost of a certain number of weak operation cells such as adders or delay elements. A FIR filter of 2 parallel 36-tap with the structure of 3-stage cascade （2 × 3 ×6 ） only needs 18 multiplies, which saves 67% the number of multiplies compared with the structure based on single stage ISCA algorithms. So, the new structure better suits parallel FIRs implementing with VLSI.